 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HC705E5GRS/D Datasheet(PDF) 80 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
HC705E5GRS/D Datasheet(HTML) 80 Page - NXP Semiconductors |
|
|
80 / 148 page  Motorola Bus (M Bus) Interface General Release Specification MC68HC705E5 — Rev. 1.0 Motorola Bus (M Bus) Interface 11.6.2 M-Bus Frequency Divider Register Bit 0–Bit 4 These bits are used for clock rate selection. The serial bit clock frequency is equal to the CPU clock divided by the divider shown in Table 11-1. This register is cleared upon reset. For a 4-MHz external crystal operation (2-MHz internal operating frequency), the serial bit clock frequency of the M-bus ranges from 460 Hz to 90,909 Hz. Address: $0019 Bit 7 654321 Bit 0 Read: FD4 FD3 FD2 FD1 FD0 Write: Reset: — — — 0 0000 = Unimplemented Figure 11-5. M-Bus Frequency Divider Register (MFDR) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
