HC705E5GRSSLASHD datasheet(48/148 Pages) NXP

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Operating Modes

General Release Specification

MC68HC705E5 — Rev. 1.0

Operating Modes

6.3 Single-Chip Mode

In single-chip mode, the address and data buses are not available

externally, but there are two 8-bit input/output (I/O) ports and one 4-bit

I/O port. This mode allows the MCU to function as a self-contained

microcontroller, with maximum use of the pins for on-chip peripheral

functions. All address and data activity occurs within the MCU.

Single-chip mode is entered on the rising edge of RESET if the IRQ pin

is within normal operating range.

Refer to Figure 1-2 for the single-chip user mode pinout diagram.

6.4 Self-Check Mode

The self-check mode provides an internal check to determine if the

device is functional.

6.5 Low-Power Modes

The following subsections provide a description of the low-power modes.

6.5.1 Stop Mode

The STOP instruction places the MCU in its lowest power-consumption

mode. In stop mode, the internal oscillator is turned off, halting all

internal processing, including timer (and COP watchdog timer)

operation.

During stop mode, the I bit in the CCR is cleared to enable external

interrupts. All other registers, including the bits in the TCSR, and

memory remain unaltered. All input/output lines remain unchanged. The

processor can be brought out of stop mode only by an external interrupt

or RESET.

The STOP instruction can be disabled by a mask option. When disabled,

the STOP instruction causes a chip reset.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 48 Page - NXP Semiconductors