HC705E5GRSSLASHD datasheet(98/148 Pages) NXP

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Synchronous Serial Interface (SSI)

General Release Specification

MC68HC705E5 — Rev. 1.0

Synchronous Serial Interface (SSI)

12.3 SSI Signals

The following sections describe the SSI signals.

12.3.1 Serial Clock (SCK)

In master mode (MSTR = 1), the SCK pin is an output with a selectable

frequency of:

fop divided by 16 (SR1:SR0 = 00),

fop divided by 8 (SR1:SR0 = 01),

fop divided by 4 (SR1:SR0 = 10), or

fop divided by 2 (SR1:SR0 = 11).

This pin will be high (CPOL = 1) or low (CPOL = 0) between

transmissions.

In slave mode (MSTR = 0), the SCK pin is an input and the clock must

be supplied by an external master with a maximum frequency of fop

divided by 2. There is no minimum SCK frequency. This pin should be

driven high (CPOL = 1) or low (CPOL = 0) between transmissions by the

external master and must be stable before the SSI is first enabled

(SE = 1).

NOTE:

Data is always captured with the SDIO pin on the rising edge of SCK.

Data is always shifted out and presented at the SDIO pin on the falling

edge of SCK.

12.3.2 Serial Data Input/Output (SDIO)

This pin receives and transmits data to or from the SSI module as

described in the following paragraphs.

SDIO as an Output Pin

Prior to enabling the SSI (SE = 0), the SDIO pin will be three-stated.

The SDIO pin will be active when the SSI is enabled (SE = 1), the

serial direction (SDIR = 1) bit is set, and MSTR = 1. The state of the

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HC705E5GRS/D Datasheet(PDF) 98 Page - NXP Semiconductors