HC705E5GRSSLASHD datasheet(65/148 Pages) NXP

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Phase-Locked Loop (PLL) Synthesis

Operation During Stop Mode

MC68HC705E5 — Rev. 1.0

General Release Specification

Phase-Locked Loop (PLL) Synthesis

9.4 Operation During Stop Mode

The PLL is switched to low-frequency bus rate and is temporarily turned

off when STOP is executed. Coming out of stop mode with an external

IRQ, the PLL is turned on with the same configuration it had before going

into STOP, with the exception of BCS which is reset. Otherwise, the PLL

control register is in the reset condition.

9.5 Noise Immunity

The MCU should be insulated as much as possible from noise in the

system. We recommend the following steps be taken to help prevent

problems due to noise injection.

1. The application environment should be designed so that the MCU

is not near signal traces which switch often, such as a clock signal.

2. The oscillator circuit for the MCU should be placed as close as

possible to the OSC1 and OSC2 pins on the MCU.

3. All power pins should be filtered (to minimize noise on these

signals) by using bypass capacitors placed as close as possible to

the MCU.

See the application note

Designing for Electromagnetic Compatibility

(EMC) with HCMOS Microcontrollers available through the Motorola

Literature Distribution Center, Motorola document number AN1050/D.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 65 Page - NXP Semiconductors