PIC18F6310ESLASHPTSQTP datasheet(69/404 Pages) MICROCHIP

69 / 404 page

 2004 Microchip Technology Inc.

Preliminary

DS39635A-page 67

PIC18F6310/6410/8310/8410

5.2

PIC18 Instruction Cycle

5.2.1

CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Internally, the program counter is

incremented on every Q1; the instruction is fetched

from the program memory and latched into the instruc-

tion register during Q4. The instruction is decoded and

executed during the following Q1 through Q4. The

clocks and instruction execution flow are shown in

Figure 5-4.

5.2.2

INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles, Q1

through Q4. The instruction fetch and execute are pipe-

lined in such a manner that a fetch takes one instruc-

tion cycle, while the decode and execute take another

instruction cycle. However, due to the pipelining, each

instruction effectively executes in one cycle. If an

instruction causes the program counter to change (e.g.,

GOTO

), then two cycles are required to complete the

instruction (Example 5-3).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 5-4:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 5-3:

INSTRUCTION PIPELINE FLOW

OSC1

OSC2/CLKO

(RC mode)

PC + 2

PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. BRA

SUB_1

Fetch 3

Execute 3

4. BSF

PORTA, BIT3 (Forced NOP)

Fetch 4

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

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