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PIC18F6310E/PTSQTP Datasheet(PDF) 12 Page - Microchip Technology |
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PIC18F6310E/PTSQTP Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 404 page ![]() PIC18F6310/6410/8310/8410 DS39635A-page 10 Preliminary 2004 Microchip Technology Inc. FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM Instruction Decode and Control PORTA PORTB PORTC RA4/T0CKI RA5/AN4/HLVDIN RB0/INT0 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0 RB1/INT1 Data Latch Data Memory (8/16 Kbytes) Address Latch Data Address<12> 12 Access BSR FSR0 FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (48/64 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 RB2/INT2 RB3/INT3 PCLATU PCU PORTD RD7/PSP7:RD0/PSP0 OSC2/CLKO(3)/RA6 Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RE7 when CCP2MX is not set. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD EUSART1 Comparators MSSP Timer2 Timer1 Timer3 Timer0 HLVD CCP1 BOR ADC 10-bit W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(3) OSC2(3) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR(2) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO OSC1/CLKI(3)/RA7 PORTE RE0/RD RE1/WR RE2/CS RE3 RE4 RE5 RE6 RE7/CCP2(1) PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF RF6/AN11 RF7/SS PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3 RG4 RG5(2)/MCLR/VPP AUSART2 CCP2 ROM Latch CCP3 |
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