PIC18F6310ESLASHPTSQTP datasheet(87/404 Pages) MICROCHIP

87 / 404 page

 2004 Microchip Technology Inc.

Preliminary

DS39635A-page 85

PIC18F6310/6410/8310/8410

6.0

PROGRAM MEMORY

For PIC18FX310/X410 devices, the on-chip program

memory is implemented as read-only memory. It is

readable over the entire VDD range during normal

operation; it cannot be written to or erased. Reads from

program memory are executed one byte at a time.

PIC18F8410 devices also implement the ability to read,

write to and execute code from external memory

devices using the external memory interface. In this

implementation, external memory is used as all or part

of the program memory space. The operation of the

physical interface is discussed in Section 7.0 “External

Memory Interface”.

In all devices, a value written to the program memory

space does not need to be a valid instruction.

Executing a program memory location that forms an

invalid instruction results in a NOP.

6.1

Table Reads and Table Writes

To read and write to the program memory space, there

are two operations that allow the processor to move

bytes between the program memory space and the

data RAM: table read (TBLRD) and table write (TBLWT).

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program

memory and places it into the data RAM space. Table

write operations place data from the data memory

space on the external data bus. The actual process of

writing the data to the particular memory device is

determined by the requirements of the device itself.

Figure 6-1 shows the table operations as they relate to

program memory and data RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word-aligned. Therefore, a table block

can start and end at any byte address. If a table write is

being used to write executable code into an external

program memory, program instructions will need to be

word-aligned.

FIGURE 6-1:

TABLE READ AND TABLE WRITE OPERATIONS

Note:

Although it cannot be used in PIC18F6310

devices in normal operation, the TBLWT

instruction is still implemented in the

instruction set. Executing the instruction

takes two instruction cycles, but effectively

results in a NOP.

The TBLWT instruction is available in

programming modes and is used during

In-Circuit Serial Programming (ICSP).

Table Pointer(1)

Table Latch (8-bit)

Program Memory Space

TBLPTRH TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1:

Table Pointer register points to a byte in the program memory space.

Data is actually written to the memory location by the memory write algorithm. See Section 6.4

“Writing to Program Memory Space (PIC18F8310/8410 only)” for more information.

Table Pointer(1)

Table Latch (8-bit)(2)

TBLPTRH TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLWT*

Program Memory Space

Data Memory Space

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