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PIC18F6310E/PTSQTP Datasheet(PDF) 76 Page - Microchip Technology |
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PIC18F6310E/PTSQTP Datasheet(HTML) 76 Page - Microchip Technology |
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76 / 404 page  PIC18F6310/6410/8310/8410 DS39635A-page 74 Preliminary 2004 Microchip Technology Inc. TMR0H Timer0 Register High Byte 0000 0000 58, 145 TMR0L Timer0 Register Low Byte xxxx xxxx 58, 145 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 58, 143 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 36, 58 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 58, 265 WDTCON — — — — — — —SWDTEN ---- ---0 58, 280 RCON IPEN SBOREN(1) —RI TO PD POR BOR 0q-1 11q0 50, 58, 115 TMR1H Timer1 Register High Byte xxxx xxxx 58, 151 TMR1L Timer1 Register Low Byte 0000 0000 58, 151 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 58, 147 TMR2 Timer2 Register 1111 1111 58, 154 PR2 Timer2 Period Register -000 0000 58, 154 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 58, 153 SSPBUF SSP Receive Buffer/Transmit Register 0000 0000 58, 170, 178 SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 58, 178 SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 58, 170, 179 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 58, 171, 180 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 58, 181 ADRESH A/D Result Register High Byte xxxx xxxx 58, 254 ADRESL A/D Result Register Low Byte 0000 0000 58, 254 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 58, 245 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 qqqq 58, 246 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 58, 247 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 59, 160 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 59, 160 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 59, 159 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 59, 160 CCPR2L Capture/Compare/PWM Register 2 Low Byte 0000 0000 59, 160 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 59, 159 CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 59, 160 CCPR3L Capture/Compare/PWM Register 3 Low Byte 0000 0000 59, 160 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 59, 159 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 59, 261 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 59, 255 TMR3H Timer3 Register High Byte 0000 0000 59, 157 TMR3L Timer3 Register Low Byte 0000 0000 59, 157 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 59, 155 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 59, 141 TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software or by a POR. |
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