PIC18F6410ESLASHPTSQTP datasheet(136/404 Pages) MICROCHIP

136 / 404 page

PIC18F6310/6410/8310/8410

DS39635A-page 134

Preliminary

 2004 Microchip Technology Inc.

10.7

PORTG, TRISG and

LATG Registers

PORTG is a 6-bit wide, bidirectional port. The corre-

sponding data direction register is TRISG. Setting a

TRISG bit (= 1) will make the corresponding PORTG

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISG bit (= 0)

will make the corresponding PORTG pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATG) is also memory

mapped. Read-modify-write operations on the LATG

PORTG.

PORTG

multiplexed

with

USART

functions

(Table 10-13). PORTG pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTG pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the

corresponding peripheral section for the correct TRIS

bit settings. The pin override value is not loaded into

the TRIS register. This allows read-modify-write of the

TRIS register without concern due to peripheral

overrides.

The sixth pin of PORTG (RG5/MCLR/VPP) is an input

only pin. Its operation is controlled by the MCLRE

configuration bit. When selected as a port pin

(MCLRE = 0), it functions as a digital input only pin; as

such, it does not have TRIS or LAT bits associated with

its operation. Otherwise, it functions as the device’s

Master Clear input. In either configuration, RG5 also

functions as the programming voltage input during

programming.

EXAMPLE 10-7:

INITIALIZING PORTG

Note:

On a Power-on Reset, RG5 is enabled as

a digital input only if Master Clear

functionality is disabled. All other 5 pins

are configured as digital inputs.

CLRF

PORTG

; Initialize PORTG by

; clearing output

; data latches

CLRF

LATG

; Alternate method

; to clear output

; data latches

MOVLW

0x04

; Value used to

; initialize data

; direction

MOVWF

TRISG

; Set RG1:RG0 as outputs

; RG2 as input

; RG4:RG3 as inputs

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