P87LPC778FDH datasheet(41/79 Pages) PHILIPS

41 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

41 of 79

9397 750 12378

8.10.7

CPU clock modiﬁcation: CLKR and DIVM

For backward compatibility, the CLKR conﬁguration bit allows setting the P87LPC778

instruction and peripheral timing to match standard 80C51 timing by dividing the CPU

clock by two. Default timing for the P87LPC778 is 6 CPU clocks per machine cycle

while standard 80C51 timing is 12 clocks per machine cycle. This division also

applies to peripheral timing, allowing 80C51 code that is oscillator frequency and/or

timer rate dependent. The CLKR bit is located in the EPROM conﬁguration register

UCFG1, described under Section 8.18 “EPROM characteristics” on page 66.

The oscillator must be conﬁgured in the External Clock input mode. A clock output may be

obtained on the X2 pin by setting the ENCLK bit in the P2M1 register.

Fig 15. Using an external clock input.

002aaa633

87LPC778

CMOS compatible

external oscillator signal

Fig 16. Block diagram of oscillator control

002aaa634

FOSC2 (UCFG1.2)

FOSC1 (UCFG1.1)

FOSC0 (UCFG1.0)

CLOCK SELECT

XTAL

SELECT

CLOCK

OUT

CLOCK

SOURCES

external

clock input

internal RC

oscillator

crystal: low

frequency

crystal: medium

frequency

crystal: high

frequency

power monitor reset

power down

10-BIT RIPPLE COUNTER

oscillator startup timer

DIVIDE-BY-M

(DIVM REGISTER) AND

CLKR SELECT

COUNT 256

CLKR

(UCFG1.3)

RESET

COUNT

COUNT 1024

÷1 / ÷2

CPU

clock

P87LPC778FDH Datasheet(PDF) 41 Page - NXP Semiconductors

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