P87LPC778FDH datasheet(28/79 Pages) PHILIPS

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Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

28 of 79

9397 750 12378

8.7.2

Reading I2CON

RDAT — The data from SDA is captured into ‘Receive DATa’ whenever a rising edge

occurs on SCL. RDAT is also available (with seven low-order zeros) in the I2DAT

clears DRDY, allowing the I2C-bus to proceed on to another bit. Typically, the ﬁrst

seven bits of a received byte are read from I2DAT, while the 8th is read here. Then

I2DAT can be written to send the Acknowledge bit and clear DRDY.

ATN — ‘ATteNtion’ is ‘1’ when one or more of DRDY, ARL, STR, or STP is ‘1’. Thus,

ATN comprises a single bit that can be tested to release the I2C-bus service routine

from a ‘wait loop.’

DRDY — ‘Data ReaDY’ (and thus ATN) is set when a rising edge occurs on SCL,

except at idle slave. DRDY is cleared by writing CDR = 1, or by writing or reading the

I2DAT register. The following low period on SCL is stretched until the program

responds by clearing DRDY.

8.7.3

Checking ATN and DRDY

When a program detects ATN = 1, it should next check DRDY. If DRDY = 1, then if it

receives the last bit, it should capture the data from RDAT (in I2DAT or I2CON). Next,

if the next bit is to be sent, it should be written to I2DAT. One way or another, it should

clear DRDY and then return to monitoring ATN. Note that if any of ARL, STR, or STP

is set, clearing DRDY will not release SCL to HIGH, so that the I2C-bus will not go on

to the next bit. If a program detects ATN = 1, and DRDY = 0, it should go on to

examine ARL, STR, and STP.

Table 24:

I2CON - I2C-bus control register (address D8H) bit description

Bit Symbol

Access Description

RDAT

The most recently received data bit

CXA

Clears the transmit active ﬂag

ATN

ATN = 1 if any of the ﬂags DRDY, ARL, STP, or STP = 1

IDLE

In the I2C-bus slave mode, writing a ‘1’ to this bit causes the I2C-bus

hardware to ignore the bus until it is needed again

DRDY

Data Ready ﬂag, set when there is a rising edge on SCL

CDR

Writing a ‘1’ to this bit clears the DRDY ﬂag

ARL

Arbitration Loss ﬂag, set when arbitration is lost while in the transmit

mode

CARL

Writing a ‘1’ to this bit clears the CARL ﬂag

STR

Start ﬂag, set when a start condition is detected at a master or

non-idle slave

CSTR

Writing a ‘1’ to this bit clears the STR ﬂag

STP

Stop ﬂag, set when a stop condition is detected at a master or

non-idle slave

CSTP

Writing a ‘1’ to this bit clears the STP ﬂag

MASTER R

Indicates whether this device is currently as bus master

XSTR

Writing a ‘1’ to this bit causes a repeated start condition to be

generated

Undeﬁned

XSTP

Writing a ‘1’ to this bit causes a stop condition to be generated

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