P87LPC778FDH datasheet(32/79 Pages) PHILIPS

32 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

32 of 79

9397 750 12378

8.8 Interrupts

The P87LPC778 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the P87LPC778’s many interrupt sources. The

P87LPC778 supports up to 13 interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA,

which disables all interrupts at once.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service

routine in progress can be interrupted by a higher priority interrupt, but not by another

interrupt of the same or lower priority. The highest priority interrupt service cannot be

interrupted by any other interrupt source. So, if two requests of different priority levels

are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are received simultaneously, an internal polling

sequence determines which request is serviced. This is called the arbitration ranking.

Note that the arbitration ranking is only used to resolve simultaneous requests of the

same priority level.

Table 29:

Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER

SLAVEN,

MASTRQ,

MASTER

TIRUN

OPERATING MODE

All 0

The I2C-bus interface is disabled. Timer I is cleared and

does not run. This is the state assumed after a reset. If

an I2C-bus application wants to ignore the I2C-bus at

certain times, it should write SLAVEN, MASTRQ, and

TIRUN all to zero.

All 0

The I2C-bus interface is disabled.

Any or all 1

The I2C-bus interface is enabled. The 3 low-order bits

of Timer I run for min-time generation, but the hi-order

bits do not, so that there is no checking for I2C-bus

being ‘hung.’ This conﬁguration can be used for very

slow I2C-bus operation.

Any or all 1

The I2C-bus interface is enabled. Timer I runs during

frames on the I2C-bus, and is cleared by transitions on

SCL, and by Start and Stop conditions. This is the

normal state for I2C-bus operation.

Table 30:

CT1, CT0 values

CT1, CT0

Min Time Count

(Machine Cycles)

CPU Clock Max

(for 100 kHz I2C-bus)

Timeout Period

(Machine Cycles)

1 0

8.4 MHz

1023

0 1

7.2 MHz

1022

0 0

6.0 MHz

1021

1 1

4.8 MHz

1020

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