P87LPC778FDH datasheet(15/79 Pages) PHILIPS

15 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

15 of 79

9397 750 12378

8.4.1

The A/D in Power-down and Idle modes

While using the CPU clock as the A/D clock source, the Idle mode may be used to

conserve power and/or to minimize system noise during the conversion. CPU

operation will resume and Idle mode terminate automatically when a conversion is

complete if the A/D interrupt is active. In Idle mode, noise from the CPU itself is

eliminated, but noise from the oscillator and any other on-chip peripherals that are

running will remain.

The CPU may be put into Power-down mode when the A/D is clocked by the on-chip

RC oscillator (RCCLK = 1). This mode gives the best possible A/D accuracy by

eliminating most on-chip noise sources.

If the Power-down mode is entered while the A/D is running from the CPU clock

(RCCLK = 0), the A/D will abort operation and will not wake up the CPU. The

contents of DAC0 will be invalid when operation does resume.

When an A/D conversion is started, Power-down or Idle mode must be activated

within two machine cycles in order to have the most accurate A/D result. These two

machine cycles are counted at the CPU clock rate. When using the A/D with either

Power-down or Idle mode, care must be taken to insure that the CPU is not restarted

by another interrupt until the A/D conversion is complete. The possible causes of

wake-up are different in Power-down and Idle modes.

A/D accuracy is also affected by noise generated elsewhere in the application, power

supply noise, and power supply regulation. Since the P87LPC778 power pins are

also used as the A/D reference and supply, the power supply has a very direct affect

Table 8:

Example A/D conversion times

CPU clock rate

RCCLK = 0

RCCLK = 1

minimum

nominal

maximum

32 kHz

563.4

µs

659

µs

757

µs

1 MHz

186

µs

32.4

µs

39.3

µs

48.9

µs

4 MHz

46.5

µs

18.9

µs

23.6

µs

30.1

µs

11.0592 MHz

16.8

µs16 µs

20.2

µs

27.1

µs

12 MHz

15.5

µs

15.9

µs

20.1

µs

26.9

µs

16 MHz

11.6

µs

15.5

µs

19.7

µs

26.4

µs

20 MHz

9.3

µs

15.3

µs

19.4

µs

26.1

µs

Fig 5.

A/D converter connections.

002aaa616

AD0 (P0.3)

AD1 (P0.4)

A/D CONVERTER

AD2 (P0.5)

AD3 (P0.6)

ADCON

DAC0

ADCON

DAC0

(A/D result, read DAC0)

VREF+ = VDD

VREF- = VSS

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