HD404828RFS datasheet(44/149 Pages) RENESAS

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HD404829R Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 26. As shown in table 16, a ceramic

oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and

X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock

select register (SSR: $029) must be set according to the frequency of the oscillator connected to OSC1 and

OSC2 (figure 27).

Note:

If the system clock select register (SSR: $029) setting does not match the oscillator frequency,

DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.

OSC2

OSC1

System

clock

oscillator

Sub-

system

clock

oscillator

1/4

division

circuit

Timing

generation

circuit

System

clock

selection

circuit

CPU with ROM,

RAM, registers,

flags, and I/O

Internal

peripheral

module

interrupt

(other than timer A)

Time A

interrupt

Clock

Time-base

clock

selection

circuit

1/8 or 1/4

division

circuit

Timing

generation

circuit

Timing

generation

circuit

1/8

division

circuit

fSUB

tsubcyc

LSON

TMA3 bit

fcyc

tcyc

fOSC

tWcyc

øCPU

øPER

øCLK

Note: *

1/8 or 1/4 division ratio can be selected by setting bit 2 of the system

clock select register (SSR: $029).

Figure 26 Clock Generation Circuit

HD404828RFS Datasheet(PDF) 44 Page - Renesas Technology Corp

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