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HD404828RFS Datasheet(PDF) 45 Page - Renesas Technology Corp |
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HD404828RFS Datasheet(HTML) 45 Page - Renesas Technology Corp |
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45 / 149 page  HD404829R Series 43 Bit Initial value Read/Write Bit name 3 0 W SSR3 2 0 W SSR2 0 — — — 1 — — — System clock select register (SSR: $029) SSR2 0 1 ratio selection fSUB = fX/8 fSUB = fX/4 SSR3 0 1 32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode SSR1 0 1 System clock selection fOSC = 400 kHz to 1 MHz fOSC = 1.6 to 4.2 MHz 32-kHz oscillation division Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input duringstop mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode. Figure 27 System Clock Select Register (SSR) D0 GND X2 X1 RESET OSC2 OSC1 TEST AVSS GND Figure 28 Typical Layouts of Crystal and Ceramic Oscillator |
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