MC908QT4MPE datasheet(111/184 Pages) FREESCALE

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Exception Control

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

111

Figure 13-8

. Interrupt Entry

Figure 13-9. Interrupt Recovery

13.6.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after

completion of the current instruction. When the current instruction is complete, the SIM checks all pending

hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the

corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next

instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is

serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt

is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the

LDA instruction is executed.

The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.

However, in the case of the INT1 RTI prefetch, this is a redundant operation.

NOTE

To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

modifies the H register or uses the indexed addressing mode, software

should save the H register and then restore it prior to exiting the routine.

MODULE

DATA BUS

R/W

INTERRUPT

DUMMY

SP – 1

SP – 2

SP – 3

SP – 4

VECT H

VECT L

START ADDR

ADDRESS BUS

DUMMY

PC – 1[7:0] PC – 1[15:8]

CCR

V DATA H

V DATA L

OPCODE

I BIT

MODULE

DATA BUS

R/W

INTERRUPT

SP – 4

SP – 3

SP – 2

SP – 1

PC + 1

ADDRESS BUS

CCR

PC – 1[7:0] PC – 1[15:8] OPCODE

OPERAND

I BIT

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