MC908QT4MPE datasheet(112/184 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908QY/QT Family Data Sheet, Rev. 5

112

Freescale Semiconductor

Figure 13-10

. Interrupt Recognition Example

13.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the

interrupt mask (I bit) in the condition code register.

NOTE

A software interrupt pushes PC onto the stack. A software interrupt does

not push PC – 1, as a hardware interrupt does.

13.6.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the

interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be

useful for debugging.

Table 13-3. Interrupt Sources

Priority

Source

Flag

Mask(1)

1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI

instruction.

INT

Flag

Vector

Address

Highest

Lowest

Reset

—

$FFFE–$FFFF

SWI instruction

—

$FFFC–$FFFD

IRQ pin

IRQF

IMASK

IF1

$FFFA–$FFFB

Timer channel 0 interrupt

CH0F

CH0IE

IF3

$FFF6–$FFF7

Timer channel 1 interrupt

CH1F

CH1IE

IF4

$FFF4–$FFF5

Timer overflow interrupt

TOF

TOIE

IF5

$FFF2–$FFF3

Keyboard interrupt

KEYF

IMASKK

IF14

$FFE0–$FFE1

ADC conversion complete interrupt

COCO

AIEN

IF15

$FFDE–$FFDF

CLI

LDA

INT1

PULH

RTI

INT2

BACKGROUND ROUTINE

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

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