MC908QT4MPE datasheet(108/184 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908QY/QT Family Data Sheet, Rev. 5

108

Freescale Semiconductor

13.4.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an

internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down

the RST pin for all internal reset sources.

To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears

the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least

every 4080 BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible

out of reset to guarantee the maximum amount of time before the first time out.

The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break

auxiliary register (BRKAR).

13.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP

bit in the SIM reset status register (SRSR) and causes a reset.

If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an

illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal

reset sources.

13.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the

CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and

resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively

pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges.

13.4.2.5 Low-Voltage Inhibit (LVI) Reset

The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI

bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the

SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4

cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.

The SIM actively pulls down the (RST) pin for all internal reset sources.

13.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the

oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as

a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for

counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP

module. The SIM counter is clocked by the falling edge of BUSCLKX4.

13.5.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit

asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock

state machine.

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