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MC908QT4MPE Datasheet(PDF) 127 Page - Freescale Semiconductor, Inc |
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MC908QT4MPE Datasheet(HTML) 127 Page - Freescale Semiconductor, Inc |
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127 / 184 page ![]() Input/Output Registers MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor 127 14.9.1 TIM Status and Control Register The TIM status and control register (TSC) does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. When the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared. When using TSTOP to stop the timer counter, see if any timer flags are set. If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the flag, then setting TSTOP again. Address: $0020 Bit 7 654321 Bit 0 Read: TOF TOIE TSTOP 00 PS2 PS1 PS0 Write: 0 TRST Reset: 00100000 = Unimplemented Figure 14-4. TIM Status and Control Register (TSC) |
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