MC908QT4MPE datasheet(130/184 Pages) FREESCALE

130 / 184 page

Timer Interface Module (TIM)

MC68HC908QY/QT Family Data Sheet, Rev. 5

130

Freescale Semiconductor

CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set when an active edge occurs on

the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the

TIM counter registers matches the value in the TIM channel x registers.

Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing

a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing

a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing

of CHxF.

Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.

1 = Input capture or output compare on channel x

0 = No input capture or output compare on channel x

CHxIE — Channel x Interrupt Enable Bit

This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE

bit.

1 = Channel x CPU interrupt requests enabled

0 = Channel x CPU interrupt requests disabled

MSxB — Mode Select Bit B

This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM

channel 0 status and control register.

Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose

I/O.

Reset clears the MSxB bit.

1 = Buffered output compare/PWM operation enabled

0 = Buffered output compare/PWM operation disabled

MSxA — Mode Select Bit A

When ELSxB:A

≠ 00, this read/write bit selects either input capture operation or unbuffered output

compare/PWM operation. See Table 14-3.

1 = Unbuffered output compare/PWM operation

0 = Input capture operation

Address: $0025

TSC0

Bit 7

654321

Bit 0

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

00000000

Address: $0028

TSC1

Bit 7

654321

Bit 0

Read:

CH1F

CH1IE

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

Write:

Reset:

00000000

= Unimplemented

Figure 14-7. TIM Channel Status and Control

Registers (TSC0:TSC1)

MC908QT4MPE Datasheet(PDF) 130 Page - Freescale Semiconductor, Inc

MC908QT4MPE Datasheet(HTML) 130 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL