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WM8974GEFL/V Datasheet(PDF) 54 Page - Wolfson Microelectronics plc |
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WM8974GEFL/V Datasheet(HTML) 54 Page - Wolfson Microelectronics plc |
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54 / 87 page  WM8974 Production Data w PD Rev 4.2 March 2007 54 u-law Companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 29 u-Law Companding A-law Companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 Normalised Input 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 30 A-Law Companding AUDIO SAMPLE RATES The WM8974 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately. |
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