WM8974GEFLSLASHV datasheet(55/87 Pages) WOLFSON

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Production Data

WM8974

PD Rev 4.2 March 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Table 51 Sample Rate Control

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8974 has an on-chip phase-locked loop (PLL) circuit that can be used to:

Generate master clocks for the WM8974 audio functions from another external clock, e.g. in

telecoms applications.

Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from

an existing audio master clock.

Figure 31 shows the PLL and internal clocking arrangment on the WM8974.

The PLL can be enabled or disabled by the PLLEN register bit.

Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are

set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power management

PLLEN

PLL enable

0=PLL off

1=PLL on

Table 52 PLLEN Control Bit

Figure 31 PLL and Clock Select Circuit

WM8974GEFL/V Datasheet(PDF) 55 Page - Wolfson Microelectronics plc

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