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XM33C321ASPZR Datasheet(PDF) 71 Page - Texas Instruments |
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XM33C321ASPZR Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 113 page ![]() VDDIO PC VSS Z1 HYSTEN INENA 0 1 15 Unassigned Peripheral 01 Peripheral 15 0 1 15 Unassigned Peripheral 01 Peripheral 15 PF SHUTDOWN Wakeup WCOMP VSS VDDIO DRV Glitch Filter WUEN Wake to PMCU IO pin SHUTDOWN D Q EN D Q EN D Q EN S Q R WAKESTATE Input Logic Output Logic PIPU PIPD To analog peripheral function(s) D Q EN D Q EN D Q EN D Q EN D Q EN SHUTDOWN Latches 1 0 INV 1 0 INV PMOS NMOS DIN DOUT 0 1 15 Unassigned Peripheral 01 Peripheral 15 Hi-Z D Q EN Driver Logic S R RELEASE Q RSTN RSTN PF != 0 PC 5V tolerant open drain IO (ODIO) does not have PMOS control and pull-up resistor Figure 8-1. Superset Input/Output Diagram 8.12 Analog Modules 8.12.1 HSADC The device has two analog-to-digital converter (ADC) modules, HSADC0 and HSADC1, support fast 12-bit conversions with single-ended inputs and simultaneous sampling operation. HSADC features include: • 12-bit output resolution at 9.4Msps with greater than 11.2 ENOB • HW averaging enables 14-bit effective resolution at 587ksps • Up to 36 total external input channels • Up to 4 independent and variable length sequencers with FIFO result read out – Maps up to 4 analog channel sequences for conversion www.ti.com MSPM33C321A, MSPM33C3219 SLASFB6 – DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: MSPM33C321A MSPM33C3219 |
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