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STM32F103XC Datasheet(PDF) 104 Page - STMicroelectronics |
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STM32F103XC Datasheet(HTML) 104 Page - STMicroelectronics |
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104 / 118 page ![]() Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 104/118 5.3.19 DAC electrical specifications Table 61. DAC characteristics Symbol Parameter Min Typ Max(1) Unit Comments VDD33A Analog supply voltage 2.4 3.6 V VDD18D Digital supply voltage 1.6 1.8 2 V VREF+ Reference supply voltage 2.4 3.6 V VREF+ must always be below VDD33A VSSA Ground 0 0 V RL Resistive load with buffer ON 5 k Ω Minimum resistive load between DAC_OUT and VSSA CL Capacitive load 50 pF Maximum capacitive load at DAC_OUT pin. DAC_OUT min Lower DAC_OUT voltage with buffer ON 0.2 V It gives the maximum output excursion of the DAC it corresponds to 12-bit input code (0E0)h to (F1C)h @ VREF+ = 3.6 V and (155)h and (EAB)h @ VREF+ = 2.4 V DAC_OUT max Higher DAC_OUT voltage with buffer ON VREF+– 0.2 V V IDD DAC DC current consumption in quiescent mode (Standby mode) (in VDD18D+VDD33A+ VREF+) 425 600 µA With no load, middle code (800)H on the inputs 500 700 µA With no load, worst code (F1C)H @ VREF+ = 3.6 V in terms of DC consumption on the inputs IDDQ DAC DC current consumption in Power Down mode (in VDD18D+VDD33A+VREF+) 5 350 nA With no load. DAC DC current consumption in Power Down mode (in VDD33A+VREF+) 5 200 DNL Differential non linearity (Difference between two consecutive code-1LSB) ±0.5 LSB Given for the DAC in 10-bit configuration (B1=B0=0 always) INL Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) ±1 LSB Given for the DAC in 10-bit configuration (B1=B0=0 always) Offset Offset error (difference between measured value at Code (800)H and the ideal value = VREF+/2 ±10 mV Given for the DAC in 10-bit configuration (B1=B0=0 always) ±3 LSB Given for the DAC in 10-bit @ VREF+ = 3.6 V Gain error Gain error ±0.5 % Given for the DAC in 10-bit configuration (B1=B0=0 always) |
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