SPEAR-09-B042 datasheet(23/66 Pages) STMICROELECTRONICS

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SPEAR-09-B042

Main blocks

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Main blocks

8.1

CPU subsystem

8.1.1

Overview

The CPU sub-system includes the following blocks:

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ARM 926EJS

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Two timer channels

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Interrupt controller (32 IRQ lines)

8.1.2

CPU ARM 926EJ-S

The ARM926EJ-S processor is used, which is targeted for multi-tasking applications.

Belonging to ARM9 family of general-purpose microprocessors, it contains a memory

management unit, which provides virtual memory features, making it compliant with

WindowsCE, Linux and SymbianOS operating systems.

The ARM926EJ-S supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the

user to trade off between high performance and high code density and includes features for

efficient execution of Java byte codes.

It also uses the ARM debug architecture and includes logic to assist in software debug.

Its main features are:

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CORE fMAX 333 MHz independent programmable for each CPU

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Memory management unit

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16 Kbyte of instruction CACHE

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16 Kbyte of data CACHE

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Configurable tightly coupled memory (I/D) size through the configurable logic array

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ARM-V5TEJ instructions set architecture:

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ARM (32-bit), Thumb® (16-bit)

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DSP extensions

–JAVATM (8-bit) instructions

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AMBA bus interface

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Embedded ICE-RT

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ETM9 (embedded trace macro-cell)

SPEAR-09-B042 Datasheet(PDF) 23 Page - STMicroelectronics

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