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SPEAR-09-B042 Datasheet(PDF) 29 Page - STMicroelectronics

Part # SPEAR-09-B042
Description  SPEAr짰 BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC
PDF  66 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR-09-B042 Datasheet(HTML) 29 Page - STMicroelectronics

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8.9
Serial memory interface
The main features of SMI are listed below:
●
supports the following SPI-compatible Flash and EEPROM devices:
–
STMicroelectronics M25Pxxx, M45Pxxx
–
STMicroelectronics M95xxx, except M95040, M95020 and M95010
–ATMEL AT25Fxx
–YMC Y25Fxx
–
SST SST25LFxx
●
acts always as a SPI master and up to 2 SPI slave memory devices are supported
(through as many chip select signals), with up to 16 MB address space each
●
the SMI clock signal (SMICLK) is generated by SMI (and input to all slaves) using a
clock provided by the AHB bus
●
SMICLK
can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can be
controlled by 7 programmable bits.
8.10
JPEG (codec)
The main features of the JPEG codec are:
●
compliance with the baseline JPEG standard (ISO/IEC 10918-1)
●
single-clock per pixel encoding/decoding
●
support for up to four channels of component color
●
8-bit/channel pixel depths
●
programmable quantization tables (up to four)
●
programmable Huffman tables (two AC and two DC)
●
programmable minimum coded unit (MCU)
●
configurable JPEG headers processing
●
support for restart marker insertion
●
use of two DMA channels and of two 8 x 32-bits FIFO’s (local to the JPEG) for efficient
transferring and buffering of encoded/decoded data from/to the codec core.



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