SPEAR-09-B042 datasheet(43/66 Pages) STMICROELECTRONICS

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SPEAR-09-B042

Standard customization

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Key features

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Meets SD host controller standard specification version 2.0

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Meets SDIO card specification version 2.0

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Meets SD memory card specification draft version 2.0

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Meets SD memory card security specification version 1.01

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Meets MMC specification version 3.31 and 4.2

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Supports both DMA and Non-DMA mode of operation

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Supports MMC plus and MMC mobile

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Card detection (insertion/removal)

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Password protection of cards

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Host clock rate variable between 0 and 52 MHz

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Supports 1-bit, 4-bit and 8-bit SD modes and SPI mode

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Supports MultiMediaCard interrupt mode

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Allows card to interrupt host in 1-bit, 4-bit, 8-bit SD modes and SPI mode.

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Up to 100 Mbit/s data rate using 4 parallel data lines (sd4-bit mode)

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Up to 416 Mbit/s data rate using 8-bit parallel data lines (sd8-bit mode)

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Cyclic redundancy check CRC7 for command and CRC16 for data integrity

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Designed to work with I/O cards, read-only cards and read/write cards

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Error correction code (ECC) support for MMC4.2 cards

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Supports read wait control, suspend/resume operation

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Supports FIFO overrun and Under run condition by stopping the SD clock

9.4.3

Flexible static memory controller

Main features of the FSMC are listed below:

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Provides an interface between AHB system bus and external parallel memory devices.

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Interfaces static memory-mapped devices including RAM, ROM and synchronous burst

Flash.

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For SRAM, ROM and Flash 8/16-bit wide, external memory and data paths are

provided.

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FSMC performs only one access at a time and only one external device is accessed.

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Little-endian and big-endian memory architectures.

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AHB burst transfer handling to reduce access time to external devices.

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Supplies an independent configuration for each memory bank.

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Programmable timings to support a wide range of devices.

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Programmable wait states (up to 31).

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Programmable bus turnaround cycles (up to 15).

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Programmable output enable and write enable delays (up to 15).

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Independent chip select control for each memory bank.

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Shares the address bus and the data bus with all the external peripherals.

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Only chips selects are unique for each peripheral.

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External asynchronous wait control.

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Configurable size at reset for boot memory bank using external control pins.

SPEAR-09-B042 Datasheet(PDF) 43 Page - STMicroelectronics

SPEAR-09-B042 Datasheet(HTML) 43 Page - STMicroelectronics

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