SPEAR-09-B042 datasheet(30/66 Pages) STMICROELECTRONICS

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SPEAR-09-B042

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8.11

Cryptographic co-processor (C3)

SPEAr BASIC has an hardware cryptographic co-processor with the following features:

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Supported cryptographic algorithms:

–

Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes.

–

Data encryption standard (DES) cipher in ECB and CBC modes.

–

SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.

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Instruction driven DMA based programmable engine.

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AHB master port for data access from/to system memory.

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AHB slave port for co-processor register accesses and initial engine-setup.

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The co-processor is fully autonomous (DMA input reading, cryptographic operation

execution, DMA output writing) after being set up by the host processor.

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The co-processor executes programs written by the host in memory, it can execute an

unlimited list of programs.

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The co-processor supports hardware chaining of cryptographic blocks for optimized

execution of data-flow requiring multiple algorithms processing over the same set of

data (for example encryption + hashing on the fly).

8.12

Low jitter PLL

Within the USB Hosts and device a local low jitter PLL is provided to meet the USB2.0

specification requirements.

8.13

Main PLL

Two PLLs are provided so that the external memory bus can run at a different frequency to

the internal AHB. To reduce the system emission both the PLL are offering four operational

modes:

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Normal mode

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Fractional mode

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Double side dithering mode

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Single side dithering mode

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