SPEAR-09-B042 datasheet(33/66 Pages) STMICROELECTRONICS

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SPEAR-09-B042

Main blocks

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8.18

I2C

An I2C interface is provided. The main features are:

●

I2C v2.0 compatible.

●

Supports three modes:

–

Standard (100 Kbps)

–

Fast (400 Kbps)

–

High-speed (3.4 Mbps)

●

Master and slave mode configuration possible.

●

Bulk data transfer capability.

●

Connection with general purpose DMA is provided to reduce the CPU load.

8.19

DDR memory controller

SPEAr BASIC-STD integrates a high performance multi-channel memory controller that

supports low power DDR and DDR2 double data rate memory devices. The multi-port

architecture ensures that memory is shared efficiently among different high-bandwidth client

modules.

8.20

Reconfigurable logic array

8.20.1

Overview

The configurable logic array consists of an embedded macro where a custom project can be

implemented by mapping up to 300 K equivalent gates.

This macro is interfaced with the rest of the system by some AHB bus, some memory

channels and it has a direct connection to the ARM processor internal bus. In this way is

also possible to customize the TCM memory or add a coprocessor using this macro.

Table 11 shows the memory cuts are available to this block:

The array is also connected to 102 I/O (3.3 V capable/tolerant and 4 mA sink/source).

Table 11.

Reconfigurable logic array interfaces

Instances

Type

Word

Bit

Notes

dual port

2048

One port hard-wired to the AMBA bus for

NAND boot phase

dual port

128

Typically used for hardware accelerators

dual port

128

Typically used for hardware accelerators

dual port

2048

Generic dual port memory cuts

dual port

1024

Generic dual port memory cuts

dual port

2048

Generic dual port memory cuts

dual port

1024

Generic dual port memory cuts

single port

512

Generic single port memory cuts

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