SPEAR-09-B042 datasheet(34/66 Pages) STMICROELECTRONICS

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Main blocks

SPEAR-09-B042

34/66

The following clocks can be used in the integrated logic:

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Up to 5 external clocks provided through the device pins

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4 separate clocks from the integrated frequency synthesizer

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PLL1 frequency

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PLL2 frequency

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48 MHz (USB PLL)

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24 MHz (Main oscillator)

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32.768 KHz (RTC oscillator)

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APB clock (programmable)

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AHB clock (programmable)

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Any of the GPIOs

8.20.2

Custom project development

The flow to develop a custom project to embed in the SPEAr BASIC device is similar to the

standard ASIC flow.

The configurable logic is an empty module of the whole system-on-chip. The pinout and the

maximum number of gates are fixed. The HDL project is synthesized using a dedicated

library and post synthesis simulation is possible to verify the custom net-list.

The verification procedure, after place and route phase, is the same as standard ASIC back

end flow.

8.20.3

Customization process

The layers used for the IP configuration range from 2 metal layers with 1 via, up to 4 metal

layers with 4 vias. Diffusion and remaining metal/vias are invariant across multiple custom

designs. Density and performance scale with the number of customization layers.

The configurable logic included in the SPEAr BASIC chip is a 300 Kgate equivalent array

when customized using 4 metals – 4 vias.

SPEAR-09-B042 Datasheet(PDF) 34 Page - STMicroelectronics