H8SLASH3024 datasheet(80/841 Pages) RENESAS

80 / 841 page

Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 42 of 800

REJ09B0260-0200

Before Execution of BCLR Instruction

P47

P46

P45

P44

P43

P42

P41

P40

Input/output

Input

Output

DDR

Execution of BCLR Instruction

BCLR #0, P4DDR

; Execute BCLR instruction on DDR

After Execution of BCLR Instruction

P47

P46

P45

P44

P43

P42

P41

P40

Input/output

Output

Input

DDR

Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since

P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.

As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR

are set to 1, making P47 and P46 output pins.

The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the

IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when

using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling

routine, for instance, it is not necessary to read the flag ahead of time.

H8/3024 Datasheet(PDF) 80 Page - Renesas Technology Corp

H8/3024 Datasheet(HTML) 80 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL