H8SLASH3024 datasheet(27/841 Pages) RENESAS

27 / 841 page

Rev. 2.00 Sep 20, 2005 page xxvii of xxxviii

Figure 9.12

Timing of Clear by Input Capture........................................................................ 291

Figure 9.13

Timing of Input Capture Input Signal.................................................................. 292

Figure 9.14

CMF Flag Setting Timing when Compare Match Occurs ................................... 292

Figure 9.15

CMFB Flag Setting Timing when Input Capture Occurs .................................... 293

Figure 9.16

Timing of OVF Setting ........................................................................................ 293

Figure 9.17

Example of Pulse Output ..................................................................................... 299

Figure 9.18

Contention between 8TCNT Write and Clear...................................................... 300

Figure 9.19

Contention between 8TCNT Write and Increment .............................................. 301

Figure 9.20

Contention between TCOR Write and Compare Match ...................................... 302

Figure 9.21

Contention between TCOR Read and Input Capture........................................... 303

Figure 9.22

Contention between Counter Clearing by Input Capture and Counter Increment 304

Figure 9.23

Contention between TCOR Write and Input Capture .......................................... 305

Figure 9.24

Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode . 306

Section 10 Programmable Timing Pattern Controller (TPC)

Figure 10.1

TPC Block Diagram ............................................................................................ 312

Figure 10.2

TPC Output Operation......................................................................................... 328

Figure 10.3

Timing of Transfer of Next Data Register Contents and Output (Example) ....... 329

Figure 10.4

Setup Procedure for Normal TPC Output (Example) .......................................... 330

Figure 10.5

Normal TPC Output Example (Five-Phase Pulse Output)................................... 331

Figure 10.6

Setup Procedure for Non-Overlapping TPC Output (Example) .......................... 332

Figure 10.7

Non-Overlapping TPC Output Example

(Four-Phase Complementary Non-Overlapping Pulse Output) ........................... 333

Figure 10.8

TPC Output Triggering by Input Capture (Example) .......................................... 334

Figure 10.9

Non-Overlapping TPC Output............................................................................. 335

Figure 10.10 Non-Overlapping Operation and NDR Write Timing ......................................... 336

Section 11 Watchdog Timer

Figure 11.1

WDT Block Diagram........................................................................................... 338

Figure 11.2

Format of Data Written to TCNT and TCSR....................................................... 344

Figure 11.3

Format of Data Written to RSTCSR.................................................................... 345

Figure 11.4

Operation in Watchdog Timer Mode ................................................................... 346

Figure 11.5

Interval Timer Operation ..................................................................................... 347

Figure 11.6

Timing of Setting of OVF.................................................................................... 347

Figure 11.7

Timing of Setting of WRST Bit and Internal Reset............................................. 348

Figure 11.8

Contention between TCNT Write and Count up ................................................. 349

Section 12 Serial Communication Interface

Figure 12.1

SCI Block Diagram.............................................................................................. 353

Figure 12.2

Data Format in Asynchronous Communication

(Example: 8-Bit Data with Parity and 2 Stop Bits).............................................. 383

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