H8SLASH3024 datasheet(31/841 Pages) RENESAS

31 / 841 page

Rev. 2.00 Sep 20, 2005 page xxxi of xxxviii

Figure 20.3

Starting and Stopping of System Clock Output ................................................... 605

Section 21 Electrical Characteristics

Figure 21.1

Darlington Pair Drive Circuit (Example)............................................................. 611

Figure 21.2

Sample LED Circuit ............................................................................................ 611

Figure 21.3

Output Load Circuit ............................................................................................. 615

Figure 21.4

Darlington Pair Drive Circuit (Example)............................................................. 622

Figure 21.5

Sample LED Circuit ............................................................................................ 622

Figure 21.6

Output Load Circuit ............................................................................................. 626

Figure 21.7

Oscillator Settling Timing.................................................................................... 631

Figure 21.8

Reset Input Timing .............................................................................................. 632

Figure 21.9

Reset Output Timing............................................................................................ 632

Figure 21.10 Interrupt Input Timing ......................................................................................... 633

Figure 21.11 Basic Bus Cycle: Two-State Access .................................................................... 634

Figure 21.12 Basic Bus Cycle: Three-State Access .................................................................. 635

Figure 21.13 Basic Bus Cycle: Three-State Access with One Wait State................................. 636

Figure 21.14 Bus-Release Mode Timing .................................................................................. 636

Figure 21.15 TPC and I/O Port Input/Output Timing ............................................................... 637

Figure 21.16 Timer Input/Output Timing ................................................................................. 637

Figure 21.17 Timer External Clock Input Timing..................................................................... 638

Figure 21.18 SCI Input Clock Timing ...................................................................................... 638

Figure 21.19 SCI Input/Output Timing in Synchronous Mode................................................. 638

Appendix C I/O Port Block Diagrams

Figure C.1

Port 1 Block Diagram........................................................................................ 754

Figure C.2

Port 2 Block Diagram........................................................................................ 755

Figure C.3

Port 3 Block Diagram........................................................................................ 756

Figure C.4

Port 4 Block Diagram........................................................................................ 757

Figure C.5

Port 5 Block Diagram........................................................................................ 758

Figure C.6 (a)

Port 6 Block Diagram (Pin P60) ........................................................................ 759

Figure C.6 (b) Port 6 Block Diagram (Pin P61) ........................................................................ 760

Figure C.6 (c)

Port 6 Block Diagram (Pin P62) ........................................................................ 761

Figure C.6 (d) Port 6 Block Diagram (Pins P63 to P66) ............................................................ 762

Figure C.6 (e)

Port 6 Block Diagram (Pin P67) ........................................................................ 763

Figure C.7 (a)

Port 7 Block Diagram (Pins P70 to P75) ............................................................ 764

Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77).......................................................... 764

Figure C.8 (a)

Port 8 Block Diagram (Pin P80) ........................................................................ 765

Figure C.8 (b) Port 8 Block Diagram (Pins P81 and P82).......................................................... 766

Figure C.8 (c)

Port 8 Block Diagram (Pin P83) ........................................................................ 767

Figure C.8 (d) Port 8 Block Diagram (Pin P84) ........................................................................ 768

Figure C.9 (a)

Port 9 Block Diagram (Pin P90) ........................................................................ 769

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