H8SLASH3024 datasheet(89/841 Pages) RENESAS

89 / 841 page

Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 51 of 800

REJ09B0260-0200

Bus-released state

Exception-handling state

Program execution state

Sleep mode

Software standby mode

Power-down state

Bus request

End of bus release

End of bus

release

Bus

request

End of

exception

handling

Exception

handling source

Interrupt source

SLEEP

instruction

with SSBY = 0

SLEEP instruction

with SSBY = 1

NMI, IRQ , IRQ ,

or IRQ interrupt

STBY="High", RES ="Low"

RES = "High"

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs

whenever

RES goes low.

From any state, a transition to hardware standby mode occurs when

STBY goes low.

Hardware standby mode*2

Reset state*1

Figure 2.13 State Transitions

2.8.4

Exception Handling Operation

Reset Exception Handling: Reset exception handling has the highest priority. The reset state is

entered when the

RES signal goes low. Reset exception handling starts after that, when RES

changes from low to high. When reset exception handling starts the CPU fetches a start address

from the exception vector table and starts program execution from that address. All interrupts,

including NMI, are disabled during the reset exception-handling sequence and immediately after it

ends.

Interrupt Exception Handling and Trap Instruction Exception Handling: When these

exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the

program counter and condition code register on the stack. Next, if the UE bit in the system control

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