H8SLASH3024 datasheet(24/841 Pages) RENESAS

24 / 841 page

Rev. 2.00 Sep 20, 2005 page xxiv of xxxviii

Figure 4.3

Reset Sequence (Modes 2 and 4) .........................................................................

Figure 4.4

Reset Sequence (Mode 6) ....................................................................................

Figure 4.5

Interrupt Sources and Number of Interrupts ........................................................

Figure 4.6

Stack after Completion of Exception Handling ...................................................

Figure 4.7

Operation when SP Value is Odd ........................................................................

Section 5 Interrupt Controller

Figure 5.1

Interrupt Controller Block Diagram.....................................................................

Figure 5.2

Block Diagram of Interrupts IRQ0 to IRQ5.......................................................... 95

Figure 5.3

Timing of Setting of IRQnF.................................................................................

Figure 5.4

Process Up to Interrupt Acceptance when UE = 1............................................... 101

Figure 5.5

Interrupt Masking State Transitions (Example)................................................... 103

Figure 5.6

Process Up to Interrupt Acceptance when UE = 0............................................... 104

Figure 5.7

Interrupt Exception Handling Sequence .............................................................. 105

Figure 5.8

Contention between Interrupt and Interrupt-Disabling Instruction...................... 107

Section 6 Bus Controller

Figure 6.1

Block Diagram of Bus Controller ........................................................................ 110

Figure 6.2

Access Area Map for Each Operating Mode ....................................................... 124

Figure 6.3

Memory Map in 16-Mbyte Mode

(H8/3024F-ZTAT, H8/3024 Mask ROM Verion) (1).......................................... 125

Figure 6.3

Memory Map in 16-Mbyte Mode

(H8/3026F-ZTAT, H8/3026 Mask ROM Verion) (2).......................................... 126

Figure 6.4

CSn Signal Output Timing (n = 0 to 7)................................................................ 129

Figure 6.5

Sample Address Output in Each Address Update Mode

(Basic Bus Interface, 3-State Space).................................................................... 130

Figure 6.6

Access Sizes and Data Alignment Control (8-Bit Access Area) ......................... 131

Figure 6.7

Access Sizes and Data Alignment Control (16-Bit Access Area) ....................... 132

Figure 6.8

Bus Control Signal Timing for 8-Bit, Three-State-Access Area ......................... 134

Figure 6.9

Bus Control Signal Timing for 8-Bit, Two-State-Access Area ........................... 135

Figure 6.10

Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)

(Byte Access to Even Address) ........................................................................... 136

Figure 6.11

Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)

(Byte Access to Odd Address)............................................................................. 137

Figure 6.12

Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)

(Word Access) ..................................................................................................... 138

Figure 6.13

Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)

(Byte Access to Even Address) ........................................................................... 139

Figure 6.14

Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)

(Byte Access to Odd Address)............................................................................. 140

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