H8SLASH3024 datasheet(98/841 Pages) RENESAS

98 / 841 page

Section 3 MCU Operating Modes

Rev. 2.00 Sep 20, 2005 page 60 of 800

REJ09B0260-0200

3.3

System Control Register (SYSCR)

SYSCR is an 8-bit register that controls the operation of the H8/3024 Group.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

SSOE

R/W

Software standby

Enables transition to software standby mode

User bit enable

Selects whether to use the UI bit in CCR

as a user bit or an interrupt mask bit

NMI edge select

Selects the valid edge

of the NMI input

RAM enable

Enables or

disables

on-chip RAM

Standby timer select 2 to 0

These bits select the waiting time at

recovery from software standby mode

Software standby

output port enable

Selects the output state

of the address bus and

bus control signals in

software standby mode

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further

information about software standby mode see section 20, Power-Down State.)

When software standby mode is exited by an external interrupt, and a transition is made to normal

operation, this bit remains set to 1. To clear this bit, write 0.

Bit 7

SSBY

Description

SLEEP instruction causes transition to sleep mode

(Initial value)

SLEEP instruction causes transition to software standby mode

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