H8SLASH3024 datasheet(26/841 Pages) RENESAS

26 / 841 page

Rev. 2.00 Sep 20, 2005 page xxvi of xxxviii

Figure 8.17

Setup Procedure for Waveform Output by Compare Match (Example) .............. 242

Figure 8.18

0 and 1 Output (TOA = 1, TOB = 0) ................................................................... 243

Figure 8.19

Toggle Output (TOA = 1, TOB = 0).................................................................... 243

Figure 8.20

Output Compare Output Timing.......................................................................... 244

Figure 8.21

Setup Procedure for Input Capture (Example)..................................................... 245

Figure 8.22

Input Capture (Example) ..................................................................................... 245

Figure 8.23

Input Capture Signal Timing ............................................................................... 246

Figure 8.24

Setup Procedure for Synchronization (Example)................................................. 247

Figure 8.25

Synchronization (Example) ................................................................................. 248

Figure 8.26

Setup Procedure for PWM Mode (Example)....................................................... 249

Figure 8.27

PWM Mode (Example 1)..................................................................................... 250

Figure 8.28

PWM Mode (Example 2)..................................................................................... 251

Figure 8.29

Setup Procedure for Phase Counting Mode (Example) ....................................... 252

Figure 8.30

Operation in Phase Counting Mode (Example) ................................................... 253

Figure 8.31

Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 253

Figure 8.32

Timing for Setting 16-Bit Timer Output Level by Writing to TOLR .................. 254

Figure 8.33

Timing of Setting of IMFA and IMFB by Compare Match................................. 255

Figure 8.34

Timing of Setting of IMFA and IMFB by Input Capture .................................... 256

Figure 8.35

Timing of Setting of OVF.................................................................................... 257

Figure 8.36

Timing of Clearing of Status Flags ...................................................................... 257

Figure 8.37

Contention between 16TCNT Write and Clear.................................................... 259

Figure 8.38

Contention between 16TCNT Word Write and Increment .................................. 260

Figure 8.39

Contention between 16TCNT Byte Write and Increment.................................... 261

Figure 8.40

Contention between General Register Write and Compare Match ...................... 262

Figure 8.41

Contention between 16TCNT Write and Overflow ............................................. 263

Figure 8.42

Contention between General Register Read and Input Capture........................... 264

Figure 8.43

Contention between Counter Clearing by Input Capture and Counter Increment 265

Figure 8.44

Contention between General Register Write and Input Capture.......................... 266

Section 9 8-Bit Timers

Figure 9.1

Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)........................... 273

Figure 9.2

8TCNT Access Operation (CPU Writes to 8TCNT, Word) ................................ 287

Figure 9.3

8TCNT Access Operation (CPU Reads 8TCNT, Word) ..................................... 287

Figure 9.4

8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte) ................... 288

Figure 9.5

8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)................... 288

Figure 9.6

8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) ........................ 288

Figure 9.7

8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte) ....................... 288

Figure 9.8

Count Timing for Internal Clock Input ................................................................ 289

Figure 9.9

Count Timing for External Clock Input (Both-Edge Detection).......................... 290

Figure 9.10

Timing of Timer Output ...................................................................................... 290

Figure 9.11

Timing of Clear by Compare Match.................................................................... 291

H8/3024 Datasheet(PDF) 26 Page - Renesas Technology Corp

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