H8SLASH3024 datasheet(103/841 Pages) RENESAS

103 / 841 page

Section 3 MCU Operating Modes

Rev. 2.00 Sep 20, 2005 page 65 of 800

REJ09B0260-0200

3.6

Memory Map in Each Operating Mode

Figures 3.1 to 3.2 show memory maps of the H8/3024 Group. In the expanded modes, the address

space is divided into eight areas.

The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.

The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode

(mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5).

The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8

and @aa:16) also differs.

3.6.1

Comparison of H8/3024 Group Memory Maps

In the H8/3024 Group, the address maps vary according to the size of the on-chip ROM and RAM.

The internal I/O register space is the same in all models. Table 3.4 shows the various address maps

in mode 5.

Table 3.4

Address Maps in Mode 5

H8/3024F-ZTAT

H8/3026F-ZTAT

H8/3024 Mask

ROM Version

H8/3026 Mask

ROM Version

Size

128 kbytes

256 kbytes

128 kbytes

256 kbytes

On-chip

ROM

Address

area

H'000000 to

H'01FFFF

H'000000 to

H'03FFFF

H'000000 to

H'01FFFF

H'000000 to

H'03FFFF

Size

4 kbytes

8 kbytes

4 kbytes

8 kbytes

On-chip

RAM

Address

area

H'FFEF20 to

H'FFFF1F

H'FFDF20 to

H'FFFF1F

H'FFEF20 to

H'FFFF1F

H'FFDF20 to

H'FFFF1F

3.6.2

Reserved Areas

The H8/3024 Group memory map includes reserved areas to which access (reading or writing) is

prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed.

Reserved Area in Internal I/O Register Space: The H8/3024 Group internal I/O register space

includes a reserved area to which access is prohibited. For details see Appendix B, Internal I/O

Registers.

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