H8SLASH3003 datasheet(709/715 Pages) RENESAS

709 / 715 page

Appendix D Pin States

D.1 Port States in Each Mode

Table D-1 Port States

Hardware Software

Bus-

Program

Reset

Standby

Released

Execution

Name

Mode

State

Mode

Sleep Mode

—

Clock output T

Clock output Clock output

A19 to A0

1 to 4

A19 to A0

D15 to D8

1 to 4

D15 to D0

AS, RD,

1 to 4

AS, RD,

HWR, LWR

P47 to P40

1 to 4

8-bit bus

keep

I/O port

D7 to D0

16-bit bus

D7 to D0

P57 to P54

1, 2

keep

I/O port

A23 to A20

3, 4

A23 to A20

P60

1 to 4

keep

I/O port*1

WAIT

P61

1 to 4

(BRLE = 0) T

I/O port

keep

BREQ

(BRLE = 1)

P62

1 to 4

(BRLE = 0)

I/O port

keep

(BRLE = 0)

(BRLE = 1)

BACK

(BRLE = 1)

P77 to P70

1 to 4

Input port

Note: * Do not set the DDR bit to 1.

Legend

High

Low

High-impedance state

keep: Input pins are in the high-impedance state; output pins maintain their previous state.

DDR: Data direction register bit

691

H8/3003 Datasheet(PDF) 709 Page - Renesas Technology Corp

H8/3003 Datasheet(HTML) 709 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL