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H8/3003 Datasheet(PDF) 711 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 711 Page - Renesas Technology Corp |
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711 / 715 page  D.2 Pin States at Reset Reset in T1 State: Figure D-1 is a timing diagram for the case in which RES goes low during the T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling of RES takes place at the fall of the system clock (ø). Figure D-1 Reset during Memory Access (Reset during T1 State) Access to external address ø Address bus CS CS to CS AS RD (read access) HWR, LWR Data bus I/O port 0 71 RES (write access) (write access) H'000000 High impedance High impedance High impedance High High High Internal reset signal T1 T2 T3 693 |
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