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H8/3003 Datasheet(PDF) 303 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 303 Page - Renesas Technology Corp |
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303 / 715 page  Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 10-2. Figure 10-2 Block Diagram of Channels 0 and 1 (for Channel 0) Clock selector Comparator Control logic TCLKA to TCLKD ø, ø/2, ø/4, ø/8 TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 Module data bus Legend TCNT: GRA, GRB: TCR: TIOR: TIER: TSR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits 2) Timer control register (8 bits) Timer I/O control register (8 bits) Timer interrupt enable register (8 bits) Timer status register (8 bits) × 285 |
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