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H8/3003 Datasheet(PDF) 304 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 304 Page - Renesas Technology Corp |
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304 / 715 page  Block Diagram of Channel 2: Figure 10-3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. Figure 10-3 Block Diagram of Channel 2 Clock selector Comparator Control logic TCLKA to TCLKD ø, ø/2, ø/4, ø/8 TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 Module data bus Legend TCNT2: GRA2, GRB2: TCR2: TIOR2: TIER2: TSR2: Timer counter 2 (16 bits) General registers A2 and B2 (input capture/output compare registers) (16 bits 2) Timer control register 2 (8 bits) Timer I/O control register 2 (8 bits) Timer interrupt enable register 2 (8 bits) × Timer status register 2 (8 bits) 286 |
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