PCIMX258CJM4A datasheet(123/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

123

3.7.20.2

USB Parallel Interface Timing

Table 96 defines the USB parallel interface signals.

Figure 97 shows the USB parallel mode transmit/receive waveform. Table 97 describes the timing

parameters (USB15–USB17) shown in the figure.

Figure 97. USB Parallel Mode Transmit/Receive Waveform

Package Information and Contact Assignment

4.1

400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch

Figure 98 shows the 17

×17 mm i.MX25 production package. The following notes apply to Figure 98:

•

All dimensions in millimeters.

•

Dimensioning and tolerancing per ASME Y14.5M-1994.

Table 96. Signal Definitions for USB Parallel Interface

Name

Direction

Signal Description

USB_Clk

Interface clock—All interface signals are synchronous to USB_Clk

USB_Data[7:0]

I/O

Bidirectional data bus, driven low by the link during idle—Bus ownership is determined by the

direction

USB_Dir

Direction—Control the direction of the data bus

USB_Stp

Out

Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus

USB_Nxt

Next—The PHY asserts this signal to throttle the data

Table 97. USB Timing Specification in Parallel Mode

Parameter

Min.

Max.

Unit

Conditions/

Reference Signal

US15

Setup time (Dir&Nxt in, Data in)

—

6.0

10 pF

US16

Hold time (Dir&Nxt in, Data in)

—

0.0

10 pF

US17

Output delay time (Stp out, Data out

—

9.0

10 pF

USB_Dir/Nxt

USB_Stp

US17

US16

USB_Data

US15

US16

US15

US17

USB_Clk

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