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MC9S08DN60F1CLF Datasheet(PDF) 267 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 267 Page - Freescale Semiconductor, Inc |
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267 / 356 page  Chapter 15 Timer/PWM Module (S08TPMV3) MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor 267 When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the TPMxCHn pin is set when the timer counter is counting down, and the channel value register matches the timer counter. If ELSnA=1, the corresponding TPMxCHn pin is set when the timer counter is counting up and the channel value register matches the timer counter; the TPMxCHn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter. Figure 15-5. High-True Pulse of a Center-Aligned PWM Figure 15-6. Low-True Pulse of a Center-Aligned PWM CHnF BIT TOF BIT ... 78 76 5 4 321 0 12 34 56 78 76 5 ... TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT ... 78 76 5 4 321 0 12 34 56 78 76 5 ... TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn |
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