MC9S08DN60F1CLF datasheet(269/356 Pages) FREESCALE

269 / 356 page

Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

269

15.3.2

TPM-Counter Registers (TPMxCNTH:TPMxCNTL)

The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.

Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where

they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or

little-endian order which makes this more friendly to various compiler implementations. The coherency

mechanism is automatically restarted by an MCU reset or any write to the timer status/control register

(TPMxSC).

Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the

TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data

involved in the write.

Table 15-3. TPM-Clock-Source Selection

CLKSB:CLKSA

TPM Clock Source to Prescaler Input

No clock selected (TPM counter disable)

Bus rate clock

Fixed system clock

External source

Table 15-4. Prescale Factor Selection

PS2:PS1:PS0

TPM Clock Source Divided-by

000

001

010

011

100

101

110

111

128

76543210

Bit 15

Bit 8

Any write to TPMxCNTH clears the 16-bit counter

Reset

00000000

Figure 15-8. TPM Counter Register High (TPMxCNTH)

MC9S08DN60F1CLF Datasheet(PDF) 269 Page - Freescale Semiconductor, Inc