MC9S08DN60F1CLF datasheet(272/356 Pages) FREESCALE

272 / 356 page

Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

272

Freescale Semiconductor

15.3.5

TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)

These read/write registers contain the captured TPM counter value of the input capture function or the

output compare value for the output compare or PWM functions. The channel registers are cleared by

reset.

MSnA

Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA conﬁgures TPM channel n for

input-capture mode or output compare mode. Refer to Table 15-6 for a summary of channel mode and setup

controls.

Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture

mode, it is possible to get an unexpected indication of an edge trigger.

3–2

ELSnB

ELSnA

Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA

and shown in Table 15-6, these bits select the polarity of the input edge that triggers an input capture event, select

the level that will be driven in response to an output compare match, or select the polarity of the PWM output.

Setting ELSnB:ELSnA to 0:0 conﬁgures the related timer pin as a general purpose I/O pin not related to any timer

functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin

available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does

not require the use of a pin.

Table 15-6. Mode, Edge, and Level Selection

CPWMS

MSnB:MSnA

ELSnB:ELSnA

Mode

Conﬁguration

Pin not used for TPM - revert to general

purpose I/O or other peripheral control

Input capture

Capture on rising edge

only

Capture on falling edge

only

Capture on rising or

falling edge

Output compare

Toggle output on

compare

Clear output on

compare

Set output on compare

Edge-aligned

PWM

High-true pulses (clear

output on compare)

Low-true pulses (set

output on compare)

Center-aligned

PWM

High-true pulses (clear

output on compare-up)

Low-true pulses (set

output on compare-up)

Table 15-5. TPMxCnSC Field Descriptions (continued)

Field

Description

MC9S08DN60F1CLF Datasheet(PDF) 272 Page - Freescale Semiconductor, Inc

MC9S08DN60F1CLF Datasheet(HTML) 272 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL