MC9S08DN60F1CLF datasheet(274/356 Pages) FREESCALE

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Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

274

Freescale Semiconductor

are used for PWM & output compare operation once normal execution resumes. Writes to the channel

registers while BDM is active do not interfere with partial completion of a coherency sequence. After the

coherency mechanism has been fully exercised, the channel registers are updated using the buffered values

written (while BDM was not active) by the user.

15.4

Functional Description

All TPM functions are associated with a central 16-bit counter which allows ﬂexible selection of the clock

source and prescale factor. There is also a 16-bit modulo register associated with the main counter.

The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM

(CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be

conﬁgured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control

bit is located in the main TPM status and control register because it affects all channels within the TPM

and inﬂuences the way the main counter operates. (In CPWM mode, the counter changes to an up/down

mode rather than the up-counting mode used for general purpose timer functions.)

The following sections describe the main counter and each of the timer operating modes (input capture,

output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and

interrupt activity depend upon the operating mode, these topics will be covered in the associated mode

explanation sections.

15.4.1

Counter

All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section

discusses selection of the clock source, end-of-count overﬂow, up-counting vs. up/down counting, and

manual counter reset.

15.4.1.1

Counter Clock Source

The 2-bit ﬁeld, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three

possible clock sources or OFF (which effectively disables the TPM). See Table 15-3. After any MCU reset,

CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These

control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA

ﬁeld) does not affect the values in the counter or other timer registers.

MC9S08DN60F1CLF Datasheet(PDF) 274 Page - Freescale Semiconductor, Inc