MC9S08DN60F1CLF datasheet(271/356 Pages) FREESCALE

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Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

271

Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the ﬁrst

counter overﬂow will occur.

15.3.4

TPM Channel n Status and Control Register (TPMxCnSC)

TPMxCnSC contains the channel-interrupt-status ﬂag and control bits used to conﬁgure the interrupt

enable, channel conﬁguration, and pin function.

76543210

Bit 7

654321

Bit 0

Reset

00000000

76543210

CHnF

CHnIE

MSnB

MSnA

ELSnB

ELSnA

Reset

00000000

= Unimplemented or Reserved

Figure 15-12. TPM Channel n Status and Control Register (TPMxCnSC)

Table 15-5. TPMxCnSC Field Descriptions

Field

Description

CHnF

Channel n ﬂag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs

on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF

is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When

channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will

not be set even when the value in the TPM counter registers matches the value in the TPM channel n value

registers.

A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by

reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs

before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence

completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous

CHnF.

Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.

0 No input capture or output compare event occurred on channel n

1 Input capture or output compare event on channel n

CHnIE

Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE.

0 Channel n interrupt requests disabled (use for software polling)

1 Channel n interrupt requests enabled

MSnB

Mode select B for TPM channel n. When CPWMS=0, MSnB=1 conﬁgures TPM channel n for edge-aligned PWM

mode. Refer to the summary of channel mode and setup controls in Table 15-6.

MC9S08DN60F1CLF Datasheet(PDF) 271 Page - Freescale Semiconductor, Inc

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