MC9S08DN60F1CLF datasheet(273/356 Pages) FREESCALE

273 / 356 page

Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

273

In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes

into a buffer where they remain latched until the other half is read. This latching mechanism also resets

(becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any

write to the channel registers will be ignored during the input capture mode.

When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register)

such that the buffer latches remain in the state they were in when the BDM became active, even if one or

both halves of the channel register are read while BDM is active. This assures that if the user was in the

middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the

other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH

and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read

buffer.

In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value

into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the

timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so:

•

If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written.

•

If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the

second byte is written and on the next change of the TPM counter (end of the prescaler counting).

•

If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after

the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1)

to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is

made when the TPM counter changes from 0xFFFE to 0xFFFF.

The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM

mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or

little-endian order which is friendly to various compiler implementations.

When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state

they were in when the BDM became active even if one or both halves of the channel register are written

while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to

the channel register while BDM is active. The values written to the channel register while BDM is active

76543210

Bit 15

Bit 8

Reset

00000000

Figure 15-13. TPM Channel Value Register High (TPMxCnVH)

76543210

Bit 7

654321

Bit 0

Reset

00000000

Figure 15-14. TPM Channel Value Register Low (TPMxCnVL)

MC9S08DN60F1CLF Datasheet(PDF) 273 Page - Freescale Semiconductor, Inc

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