MC9S08DN60F1CLF datasheet(281/356 Pages) FREESCALE

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Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

281

15.6.2.1.2

Center-Aligned PWM Case

When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to

down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF

corresponds to the end of a PWM period.

15.6.2.2

Channel Event Interrupt Description

The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,

edge-aligned PWM, or center-aligned PWM).

15.6.2.2.1

Input Capture Events

When a channel is conﬁgured as an input capture channel, the ELSnB:ELSnA control bits select no edge

(off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the

selected edge is detected, the interrupt ﬂag is set. The ﬂag is cleared by the two-step sequence described

in Section 15.6.2, “Description of Interrupt Operation.”

15.6.2.2.2

Output Compare Events

When a channel is conﬁgured as an output compare channel, the interrupt ﬂag is set each time the main

timer counter matches the 16-bit value in the channel value register. The ﬂag is cleared by the two-step

sequence described Section 15.6.2, “Description of Interrupt Operation.”

15.6.2.2.3

PWM End-of-Duty-Cycle Events

For channels conﬁgured for PWM operation there are two possibilities. When the channel is conﬁgured

for edge-aligned PWM, the channel ﬂag gets set when the timer counter matches the channel value register

which marks the end of the active duty cycle period. When the channel is conﬁgured for center-aligned

PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM

case, the channel ﬂag is set at the start and at the end of the active duty cycle period which are the times

when the timer counter matches the channel value register. The ﬂag is cleared by the two-step sequence

described Section 15.6.2, “Description of Interrupt Operation.”

15.7

The Differences from TPM v2 to TPM v3

1. Write to TPMxCNTH:L registers (Section 15.3.2, “TPM-Counter Registers

(TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7]

Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter

(TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared

in this case.

2. Read of TPMxCNTH:L registers (Section 15.3.2, “TPM-Counter Registers

(TPMxCNTH:TPMxCNTL))

— In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the

TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was

read before the BDM mode became active, then any read of TPMxCNTH:L registers during

MC9S08DN60F1CLF Datasheet(PDF) 281 Page - Freescale Semiconductor, Inc

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